This invention relates to signal detect circuitry for a high-speed serial interface, especially in a programmable logic device, and more particularly to signal detect circuitry having improved accuracy and flexibility.
PLDs frequently incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
Each transceiver typically includes signal detection circuitry in both its receiver and transceiver portions. In the receiver portion, the signal detection circuitry typically is referred to as “signal detect” or “SD,” and generates a signal that alerts the rest of the receiver to incoming data. In the transmitter portion, the signal detection circuitry typically is referred to as “receiver detect” or “RxD,” and generates a signal when it detects that transmitted signals are being received by a receiver at the other end. The same is true in serial transceivers other than those used with the XAUI standard.
Known signal detection circuits are analog, and typically incorporate a rectifier and an integrator, which produce a signal that is then compared to a reference level. However, the nature of rectification and integration is such that they cause a loss of accuracy.
Therefore, it would be desirable to be able to provide more accurate signal detection circuitry in serial interfaces, particularly on a programmable logic device.